This invention relates to a reference-column circuit for supplying a reference voltage to be used in sensing whether or not memory cells are programmed. In a specific example, the reference-column circuit is used to sense the presence or absence of charges on the floating gates of floating-gate, avalanche-injection, metal-oxide-semiconductor (FAMOS) devices that comprise an integrated-circuit logic array. The reference-voltage circuit of this invention is used in logic arrays having virtual-ground circuit connections.
Virtual-ground circuits for erasable-programmable-read-only-memory (EPROM) integrated-circuit devices are described, for example, in U.S. Pat. No. 4,151,021 issued to David J. McElroy and in U.S. Pat. No. 4,387,447 issued to Jeffrey M. Klaas, et al., both patents assigned to Texas Instruments Incorporated. Use of virtual-ground circuits in floating-gate memory arrays allows a decrease in cell size or an increase in bit density by eliminating the need for a ground line for each column or output line. "Dummy" cells, or reference column circuits, may be used with virtual ground arrangements to create a reference voltage that is used to form a sense voltage differential or margin, as described in U.S. Pat. No. 4,301,518 issued to Jeffrey M. Klaas and assigned to Texas Instruments Incorporated.
In general, the sense margin or voltage differential between a programmed (or non-programmed) read-only-memory cell output and the output of a dummy cell is controlled by varying the width-to-length ratio of certain transistor channels in the logic array in relation to the width-to-length ratio of certain transistor channels in the dummy cell.
Virtual-ground circuits in memory arrays are characterized by connection of only one output conductor to a common source-drain path terminal of two adjacent floating-gate transistors. During read operation, a reference voltage source is connected to the non-common source-drain path terminal of one of the two floating-gate transistors. The non-common source-drain terminal of the other floating-gate transistor is connected to ground or other source of reference potential. The voltage at the common node will be larger if the source-drain paths of both transistors are conductive, or not programmed, than the voltage would be without the common source-drain connection. The voltage at the common source-drain connection is used to sense the presence or absence of a programming charge on the floating gate of one of the two floating-gate transistors by comparing that voltage with the voltage output of the reference-column circuit or dummy cell.
Prior-art reference-column circuits have been comprised of a dummy cell with only one floating-gate transistor that furnishes a reference voltage for comparison with the voltage output at the common source-drain connection of the floating-gate transistors of a memory array. Because the voltage output at the common source-drain connection of the floating-gate transistors may have two values depending on whether or not the adjacent floating-gate transistor is conductive, there is a need for a reference-column circuit that will furnish a reference voltage that will not cause the sense amplifier to give an erroneous output signal if an adjacent floating-gate transistor is conductive. The same need exists for memory arrays comprised of other types of memory cells.